For further miniaturization of charge-trapping memory cells, especially of NROM (nitride read only memory) memory cells, memory transistors can be arranged on the walls of trenches etched into a semiconductor material. This arrangement significantly reduces the strong dependence of the necessary chip surface area on the thickness of the gate oxide and the channel length of the transistors, as is typical for two-dimensional components. One such semiconductor memory with vertical charge-trapping memory cells consists of a comb-like structure of the semiconductor body or substrate with channel regions in the trench walls. The channel regions are located between source/drain regions that are located at the surface on the edge of the trenches and at the base of the trenches.
Here, it is difficult to connect the bit line in the trench base. A connection must contact the bit line in the trench base and connect vertically to one of the metallization layers provided for wiring. Within the cell field, the trench for such a contact is too narrow.